论文标题:高速电流舵型CMOS数模转换器的研究与设计
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论文作者 茹纪军
论文导师 杨谟华,论文学位 硕士,论文专业 微电子与固体电子学
论文单位 电子科技大学,点击次数 123,论文页数 71页File Size10868k
2005-01-01论文网 http://www.lw23.com/lunwen_173165167/ D/A转换器; 高速; CMOS; 电流舵型
D/A converters; high speed; CMOS; current-steering
本文较为全面的研究了高速D/A转换器的设计方法及设计过程,完成了一个8位100MHz电流舵型D/A转换器的电路设计。全文共分五章,第一章简要介绍了一下本课题的来源及研制的意义,并对D/A转换器的国内外研究现状及发展趋势做了简要概括。第二章介绍了D/A转换器的基本原理及常见结构,并比较了各种结构的优缺点。第三章从系统的角度对限制电流舵型D/A转换器性能的误差源及误差产生机理做了比较全面的分析。在第三章建立的模型的基础上,第四章详细阐述了一个8位100MHz电流舵型D/A转换器的具体电路设计过程。其中包括模拟电路部分设计和数字电路部分设计,并对各个单元电路模块做了描述及仿真。总体电路的搭建及仿真的结果在第五章中给出,仿真的结果基本符合系统设计的要求。另外可测性设计以及系统的测试技术也在第五章阐述。本文系统分析了高速电流型CMOS 数模转换器的设计方法,采用了具有开关信号限幅功能的高速同步锁存电路和特殊结构的时钟驱动电路,提高了整个D/A转换器的速度。设计了一种采样率为100MHz,分辨率为8bit,电源电压为3.3v的CMOS 电流型D/A 转换器。电路仿真结果表明在采样率为100MHz,输入信号从直流到Nyquist 频率,无杂散动态范围(SFDR)为49dB.积分线性误差(INL)和微分线性误差(DNL)分别为±0.5LSB 和±0.3LSB.在采样率为100MHz,电源电压为3.3v 时的功耗小于100mw。电路采用UMC 0.35um CMOS 工艺实现。
This paper presented the general design methodology and process of high speed digital-to-analog converters and accomplished the circuit design of a 8bit 100MHz D/A converters。This paper has five chapters。First chapter the resource and meaning of this research,the trends and states for high speed D/A converters design both in China and foreign countries are included。In the second chapter,we discussed the basic theory and architecture of D/A converters,give the advantages and disadvantages between them。Analysis of the error source from the system view are added in chapter three for the current-steering D/A converters design。Based on the model of chapter three,circuit design of a 8bit 100Mz current-steering D/A converters are presented in chapter four,including analog circuit design and digital circuit design。The whole circuit architecture and simulation results are illustrated in chapter five,the design-for-test and test technique for high speed D/A converters are also discussed in this chapter。Through system analysis the design methodology of high speed current-steering D/A converters,A 3.3v 8bit 100MHz current-steering D/A converters is presented 。Simulation results show that the spurious-free-dynamic-range is better than 49dB for sampling frequency up to 100MHz and signals from dc to Nyquist frequency。Monte-Carlo simulations show that the integral non-linearity(INL) and differential non-linearity(DNL) is better than ±0.5LSB and ±0.3LSB respectively。It dissipated less than 100mW from 3.3v power supply at 100MHz sampling rate。The circuit has been designed in a UMC 0.35um CMOS process。
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