论文标题:RS（255，223）译码器的FPGA实现及其性能测试
Experimental Study and Correlation Degree Analysis on the Performance Evaluation Index of Wheat No-tillage Planter
论文作者 石俊峰
论文导师 王宇,论文学位 硕士,论文专业 飞行器设计
论文单位 中国科学院研究生院（空间科学与应用研究中心）,点击次数 146,论文页数 76页File Size1497k
2005-05-30论文网 http://www.lw23.com/lunwen_23409002/ Reed-Solomon 码;复数基;FPGA;性能测试;PCI 总线
RS code; composite basis; FPGA; Verification; PCI bus
在卫星通讯中,差错控制编码技术对降低误码率、提高通信的可靠性具有非常重要的作用。RS(Reed-Solomon)码是差错控制领域中一种性能优异的线性分组循环码,由于其具有很强的随机错误和突发错误的纠错能力,所以被CCSDS、NASA、ESA 等空间组织接受,广泛用于深空探测中。目前我国还没有高码速率的RS 硬件译码器,虽然“双星计划”已经采用RS纠错编码技术,在卫星上使用RS(255,223)硬件编码器进行编码,但是由于硬件译码器的复杂性,地面接收系统采用的是软件译码,无法保证通信的实时性。为此,本课题首先研究了常规的RS 译码器的算法,确定在关键方程的计算中采用一种新改进的BM 算法,然后提出了基于复数基的有限域快速并行乘法器和利用幂指数相减进行除法计算的有限域除法器,通过这些优化方法提高了RS译码器的速度,减少了译码延时和硬件资源使用,最后利用VHDL 硬件描述语言在FPGA 上实现了流水线处理的RS(255,223)译码器。译码器测试系统的设计和译码器性能测试是本课题另外两个重要环节。在选用合适的FPGA 完成译码器的硬件实现后,开发出了基于PCI 总线的RS 硬件译码器测试系统。利用硬件产生41 级m 序列随机数对译码器测试系统的可靠性进行验证后,针对译码器译码速度,译码延时和纠错能力等性能指标,提出了相应的几种测试方法。测试过程中,按照BPSK 系统不同的误码率给RS随机编码码块加噪的方法用于全面测试译码器的纠错能力。本课题选用XILINX 公司的FPGA 芯片XCV600E-6HQ240C 进行译码器实现。验证结果表明该译码器的码速率能达到400Mbps,译码延时为554 个时钟周期,使用FPGA 资源180,000 门,译码性能与理论上译码性能基本一致。同时该译码器译码速度还具有向下兼容的特性,而且算法易于往其他芯片移植。本课题实现的RS(255,223)硬件译码器的性能在国内具有领先水平,对我国以后航天项目高速数据传输系统的设计有着很大的意义。
Error-control coding technology is very important to reduce error probability and improve dependability in satellite communication. RS (Reed-Solomon) code is an excellent linear cyclic block code in the error-control field. It has been widely used in deep space exploration for its powerful random and burst error-correction ability, and has been adopted by NASA, ESA and CCSDS as recommended standard. RS encoding data transportation, using a RS(255,223) hardware encoder, has been adapted in our “DOUBLE STAR”exploration plan. Because of the complexity of RS hardware decoder, software decoding was used in the ground receiving system which can not guarantee real time communication. A high speed hardware RS decoder is necessary in our future projects. Having studied several kinds of RS decode algorithm, we have chosen the reformulated inversionless BM algorithm to solve the key equation of the decoder. Parallel multiplier of finite field based on composite basis and divider using exponential subtraction have been developed. By implementing the above presented approaches, not only the decoder’s speed is improved but also the decoding latency and hardware overheads are reduced. Other two important tasks of our research project include the design of the verification system and the performance test for the decoder. We have set up a test system based on PCI bus for the testing of the decoder. After verified the test system’s reliability with 41 grades m sequence random data produced by hardware, the speed, decoding latency, error-correction ability and other performance parameters of RS decoder were tested comprehensively. In the testing process, coding blocks are disturbed according to different bit-error probability of BPSK system to test the error-correcting ability of the RS decoder. The RS decoder, composed of only 180,000 gates, is realized on a XILINX FPGA (XCV600E-6HQ240C). The test results have proved that, the decoder has a
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