论文标题:DC/DC变换器并联均流与交错控制研究
Research on the Current Share and Interleaving Control of the Paralleled DC/DC Converters
论文作者 梁锋
论文导师 瞿文龙,论文学位 硕士,论文专业 电气工程
论文单位 清华大学,点击次数 624,论文页数 77页File Size1051k
2004-06-01论文网 http://www.lw23.com/lunwen_382857/ DC/DC变换器,并联系统,无均流线均流控制,无交错线自动交错
DC/DC converter, Paralleled system, Current share without current share line, Automatic interleaving without interleaving bus
较之传统的单电源供电,并联电源具有很多优点,如方便实现大容量、高效率,能够保证较高的可靠性等。而几个DC/DC电源模块并联时,如果能够实现各模块的交错运行,则可以减小总输出电压和电流的纹波幅值,提高纹波频率,从而改善输出电压和电流的质量。本文致力于DC/DC变换器并联均流及自动交错控制的研究,提出了一种无均流线均流控制及无交错线自动交错运行控制方案。该方案采用分布式控制,与现有的其他控制方案相比,其最大的特点就是各并联电源模块之间只通过输出端负载彼此相连,此外再不需要其他连接线(均流线和交错线),因此可以实现真正的模块化。本文详细介绍了所提出的无均流线均流控制的原理,并给出了控制框图。在该控制方案中,各电源模块向输出母线注入一高频低幅值正弦信号,该信号频率与本模块输出电流的幅值成反比。通过检测输出母线上的正弦信号频率的分布情况,各电源模块即可获得本系统其他模块的输出电流信息,并据此对自身的电流设定值进行调节,从而实现系统的均流控制。无交错线自动交错控制方案是本文研究的重点。文中详细阐述了该控制方案的工作原理,进行了仿真研究,并介绍了利用模拟电路实现该方案的方法。在该方案中,各电源模块通过检测输出电压中的尖峰脉冲(电压毛刺)来获得系统中其他模块的开关时序,并据此对本模块的开关信号的相位进行调整,从而实现系统的交错运行。此外,当系统中参与并联的模块数目变化时,该方案还能够自动进行调整,使系统在新的并联状态下重新达到交错状态,因而具有自动交错功能。设计、研制了一台由三个DC/DC模块并联的电源样机,对提出的无均流线均流控制方案和无交错线自动交错控制方案进行了实验研究,实验结果表明以上控制方案是可行的。
Compared with traditional single large power supply, the paralleled power systems have many obvious advantages. Due to their advantages in reliability, maintainability, flexibility and standardization, such systems have been proposed in many applications. Furthermore, if the cells paralleled in the system can be operated in an interleaving state, the input and output ripple amplitude will be decreased in a large degree with the rising of the ripple frequency. And then the quality of output voltage as well as current will be improved.Current share and interleaving control of the paralleled DC/DC converters are researched in this thesis. A kind of current share and automatic interleaving approach is proposed. In this new approach, distributed control circuits are adopted. Compared with the those existing approaches, the biggest characteristic of this approach is that, no other line between the cells is needed except the output bus, so that the system possesses high stability, and the “modularization” can be really realized.The principle of current share approach without current share line is introduced in detail, and the block diagram of the circuit is presented. In each cell, a high frequency signal is injected into the output bus to transfer the output current information of the cell, so that the current information of other cells can be known by detecting the high frequency signals in the output bus. Hence, the current reference of each cell can be regulated to realize the current share of the system. Research on automatic interleaving without interleaving bus is the main part of this thesis. The principle of the approach is described in detail. Simulations and circuit implementations are also presented. In this approach, the voltage pulses ridden on the output voltage are detected, through which the clock informations of other cells can be known. The switching signal phase of each cell is adjusted according to the switching sequences of other cells. If the cell number changes, the system can enter new state of interleaving operation automatically, so that automatic interleaving can be realized in this approach. A prototype which consists of three paralleled DC/DC converters is designed and developed. Some experiments have been made. The experimental results show that the approach proposed is feasible.
|
