论文标题:数字电视传输系统中BCH码编/译码器的研究与FPGA实现
Research and FPGA Implementation of BCH Encoder and Decoder in Digital Television Broadcasting System
论文作者
论文导师 姚冬苹,论文学位 硕士,论文专业 通信与信息系统
论文单位 北京交通大学,点击次数 141,论文页数 88页File Size8542K
2008-06-01论文网 http://www.lw23.com/lunwen_855492132/
BCH codes;; RS codes;; FPGA;; DMB-TH;; CMMB;; DVB-S2
电视节目数字化是广播电视产业发展历程上的一次重大变革,数字电视传输系统、第三代移动通信系统和新一代因特网一起构成了21世纪的三大信息基础设施。数字电视广播标准深刻影响到诸如信息服务业和发射/接收终端制造业等产业发展。数字电视将逐步与信息、通信领域的其它技术手段相互融合,从而形成全新的、庞大的数字电视产业。数字电视芯片产业的发展对我国广播电视产业的可持续发展,对我国数字电视开发、制造企业核心竞争力的提高,乃至我国综合国力都有着重要的影响。 数字电视信号在传输过程中由于受到各种信道噪声以及多径衰落等干扰因素的影响,必将产生信息失真和误码,因此为了保证数字电视信号的传输质量,数字电视传输系统中广泛使用了信道编码技术。RS码和BCH码由于良好的纠错性能,在许多数字电视标准中都得到了采用。研究发现,采用基于迭代的软判决译码算法,可以进一步提高RS码的译码性能,因此研究适合数字电视传输系统的RS码软判决译码算法很有必要。 本论文首先回顾了数字电视和信道编码理论的发展历程,随后介绍了DMB-TH、CMMB和DVB-S2三个数字电视传输系统的系统结构以及其中使用的信道编码方案;设计了基于FPGA的硬件系统平台,用以实现DMB-TH系统中BCH/RS码+LDPC码串行级联信道编/译码器;深入研究了以上三个系统中BCH/RS码的并行编/译码算法,设计并在FPGA上实现了DMB-TH系统中的并行BCH码编/译码器以及CMMB系统中的比特并行RS码编码器;设计了DMB-TH系统信道编/译码器的整体硬件测试方案,并完成了实际测试,测试结果表明编/译码器完全符合设计要求。此外,总结分析了RS码软判决译码算法的发展和研究现状,重点对其中具有代表性的Koetter-Vardy算法进行了理论研究。最后,对全文进行了总结,并对下一步研究工作予以展望。
Television program digitization is a significant transformation during the development of broadcast television industry, which is honored as a strategic technology of the new century. Digital television broadcasting system, the third generation mobile communication system and the next generation Internet, constituted three major information infrastructure of the 21st century. Digital television broadcast standard will profoundly influence the development of the information service industry, the development of transmission/reception terminal manufacturing industry,etc. Meanwhile, digital television will gradually integrate other techniques of the communication and information field so as to form a completely new and huge digital television industry. The development of digital television chip will have a significant effect on the enhancement of our technical power, and even our national strength. Error will occur during the transmission since digital television signal is interfered by various channel noises and multi-path effect. For reliable transmission of the digital television signal, technology of channel encoding has been widely used in digital television broadcasting system. BCH/RS has been employed in many digital systems" standard because they provide powerful function of error correction.. Research shows that iterative soft-decision decoding theory could improve the decoding performance of RS codes obviously. It is important and necessary to do research on suitable soft-decision algorithm of RS codes for digital television broadcasting system. In this thesis we first review the developing status and current situation of digital television broadcasting system and channel encoding theory. Channel encoding blocks in DMB-TH, CMMB and DVB-S2 systems are introduced, based on summary of the application of the channel encoding technology in digital broadcasting systems. Then we make a study on the concatenated codes of BCH/RS+LDPC in the three systems mentioned above and design the hardware platform on FPGA for the channel encoder and decoder of DMB-TH system. We also do research on parallel algorithm for the BCH/RS encoding. Parallel BCH encoder and decoder for DMB-TH system and bit-parallel RS encoder for CMMB system are designed and implemented on FPGA platform. Design of the whole channel encoder and decoder of DMB-TH system have been tested and verified on FPGA platform. In addition, we have done research on soft-decision of RS codes especially on Koetter-Vardy algorithm which is a typical algebraic soft-decision algorithm of RS codes. Finally, we summarize the whole thesis and give a further plan of the research.
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