论文标题:基于DVD应用的RS编译码器的研究和FPGA实现
论文作者
论文导师 魏廷存,论文学位 硕士,论文专业 软件工程
论文单位 西北工业大学,点击次数 111,论文页数 68页File Size5503K
2007-03-01论文网 http://www.lw23.com/lunwen_860911832/
RS code; BM algorithm; ME algorithm;Finite-field calculation; Errors and erasures correcting; DVD
纠错码技术是一种通过增加一定冗余信息来提高信息传输可靠性的有效方法。RS码是一种典型的纠错码，在线性分组码中，它具有最强的纠错能力，既能纠正随机错误，也能纠正突发错误，在深空通信、移动通信、磁盘阵列、光存储及数字视频广播(DVB)等系统中具有广泛的应用。 DVD是一种高容量的存储媒质。DVD技术的应用很广泛，在数字技术中占有重要地位。DVD系统中采用里德．所罗门乘积码(RS-PC：Reed-Solomon ProductCode)进行纠错，RS码译码器在伺服芯片中具有重要作用。 FPGA在开发阶段具有安全、方便、可随时修改设计等不可替代的优点，在电子系统中采用FPGA可以极大的提升硬件系统设计的灵活性，可靠性，同时提高硬件开发的速度和降低系统的成本。FPGA的固有优点使其得到越来越广泛的应用，FPGA设计技术也被越来越多的设计人员所掌握。 本文首先介绍了编码理论和常用的RS编译码算法，提出RS编码器实现方案，详细分析了译码器的ME算法和改进BM算法的实现，针对ME算法提出了一种流水线结构的纠删纠错RS译码器实现方案，在译码器复杂度和延时上作了折衷，降低了译码器的复杂度并提高了最高工作频率，利用有限域乘法器的特性对编译码电路进行优化。这些技术的采用大大的提高了RS编译码器的效率，节省了RS编译码器占用的资源。在Xilinx公司的Virtex-Ⅱ系列FPGA上设计并成功实现了RS(208，192)编译码器。
Error-correcting codes technology is a effective way to improve the reliability of information transmission by increasing certain redundant information. RS code is a kind of typical error-correcting codes. Among linear block codes, it has the strongest correcting capability, which can correct bursting and random errors. It is widely applied in deep space communications,mobile communications,RAID, optical storage and digital video broadcasting (DVB) system.DVD is a high-capacity storage medium.Application of DVD technology is very extensive, which occupies an important position in digital technology. The DVD system correct errors on Reed-Solomon product code (RS-PC: Reed-Solomon Product Code). RS decoder plays an important role in servo chip.FPGA has irreplaceable advantages including safe, convenient and improvable at any time in development stage.FPGA can greatly enhance the flexibility, reliability of hardware system,improve the speed and reduce the cost in electronic hardware system. FPGA"s inherent advantages can be more widely applied. FPGA design technology is also available to more designers.This paper introduced code theory and the common RS codec algorithm, the implementation of RS encoder, then detailedly analyse the decoder realization of BM algorithm and ME algorithm, then bring forward implementation and improvement of a pipeline structure errors and erasures correcting RS decoder on ME algorithm, compromise the decoder complexity and delay to reduce the complexity and raise the maximum operating frequency. Finite-field multipliers optimize codec circuit. The adoption of these technologies has greatly improved the efficiency of the RS encoder and decoder, and saved on the resources. RS(208, 192) encoder/decoder was implemented on Virtex-II FPGA of Xilinx company.
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